The demand for more compact physical arrangements of microelectronic elements such as integrated chips and dies has become even more intense with the rapid progress of portable electronic devices, the expansion of the Internet of Things, nano-scale integration, subwavelength optical integration, and more. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips and dies into a small space.
Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide. Chips and dies are commonly provided as individual, prepackaged units. In some unit designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB). Dies can be provided in packages that facilitate handling of the die during manufacture and during mounting of the die on the external substrate. For example, many dies are provided in packages suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Most commonly, such packages include a dielectric element, commonly referred to as a “chip carrier” with terminals formed as plated or etched metallic structures on the dielectric. The terminals typically are connected to the contacts (e.g., bond pads) of the die by conductive features such as thin traces extending along the die carrier and by fine leads or wires extending between the contacts of the die and the terminals or traces. In a surface mounting operation, the package may be placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is generally provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or “reflow” the solder or otherwise activate the bonding material.
Many packages include solder masses in the form of solder balls that are typically between about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, and are attached to the terminals of the package. A package having an array of solder balls projecting from its bottom surface (e.g., surface opposite the front face of the die) is commonly referred to as a ball grid array or “BGA” package. Other packages, referred to as land grid array or “LGA” packages are secured to the substrate by thin layers or lands formed from solder. Packages of this type can be quite compact. Certain packages, commonly referred to as “chip scale packages,” occupy an area of the circuit board equal to, or only slightly larger than, the area of the device incorporated in the package. This scale is advantageous in that it reduces the overall size of the assembly and permits the use of short interconnections between various devices on the substrate, which in turn limits signal propagation time between devices and thus facilitates operation of the assembly at high speeds.
Packaged semiconductor dies can also be provided in “stacked” arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow a number of different dies to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the packages. Often, this interconnect distance can be only slightly larger than the thickness of the die itself. For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., faces) of each die package (except for the topmost package). This has been done, for example, by providing contact pads or lands on both sides of the substrate to which the die is mounted, the pads being connected through the substrate by conductive vias or the like. Examples of stacked chip arrangements and interconnect structures are provided in U.S. Patent App. Pub. No. 2010/0232129, the disclosure of which is incorporated by reference herein.
Some solutions also include the use of flexible substrates and printed circuits, or folded circuit carriers. One or more v-shaped cuts, for example, can be made in a carrier and in package encapsulant, providing an edge for folding the package onto itself into a quasi-stacked arrangement. Difficulties arise due to mechanical stresses on the substrates and carriers from the bending and folding, which can lead to failure of the circuit or the package.